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\title{Unlocking the Potential of Suspend to RAM using Linux in a Multi-Core  Multi-Firmware Automotive SoC}
\authors{Gregory CLEMENT}
\email{gregory.clement@bootlin.com}
\slidesurl{https://bootlin.com/pub/conferences/2024/elc/clement-s2r-dra821.pdf}
\institute{Bootlin}
\conference{Embedded Linux Conference 2024 - Seattle}

\begin{document}
\addtocontents{toc}{\protect\setcounter{tocdepth}{-1}}
\section{Unlocking the Potential of Suspend to RAM (S2R) using Linux in a Multi-Core,  Multi-Firmware Automotive SoC}
\addtocontents{toc}{\protect\setcounter{tocdepth}{1}}

\begin{frame}{Gregory CLEMENT}
  \begin{columns}
    \column{0.6\textwidth}
    \begin{itemize}
    \item Embedded Linux engineer and trainer at Bootlin
      \begin{itemize}
      \item Embedded Linux {\bf expertise}
      \item {\bf Development}, consulting and training
      \item Strong open-source focus
      \end{itemize}
    \item Open-source contributor
      \begin{itemize}
      \item Contributing to {\bf kernel support} for the Armada 370,
        375, 38x, 39x and Armada XP ARM SoCs and Armada 3700, 7K/8K
        ARM64 SoCs from Marvell.
      \item Co-maintainer of mvebu sub-architecture (SoCs from Marvell
        Engineering Business Unit)
      \item Living near {\bf Lyon}, France
      \end{itemize}

    \end{itemize}
    \column{0.4\textwidth}
    \includegraphics[width=\textwidth]{common/logo-square.pdf}\\
  \end{columns}
\end{frame}

\begin{frame}{Fast and Furious: Accelerating Car Start-Up with Complex Socs}
  \begin{columns}
    \column{0.8\textwidth}
    \begin{itemize}
    \item User Expectation: Instant Car Readiness
    \item Car should be ready to use upon door opening
    \item Minimal tolerance for waiting time (even a dozen seconds)
    \item Complex systems require more time to boot
    \item Manufacturers are investing time and money to address this issue when using modern SoCs
    \end{itemize}
    \column{0.3\textwidth}
    \includegraphics[width=\textwidth]{car_dashboard.jpg}
    \newline
    \newline
    \includegraphics[width=\textwidth]{car_fast.jpg}
    %Photo par croperter formulaire PxHere
  \end{columns}
\end{frame}



\begin{frame}{Reducing Boot Time: Solutions and Limitations}
  \begin{itemize}
  \item Fast Boot Solutions:
    \begin{itemize}
    \item Falcon boot in U-Boot
    \item DMA to load the system while hardware is initialized
    \item And even more, see other ELC talks about it
    \end{itemize}
  \item Limitations of Fast Boot Solutions:
    \begin{itemize}
    \item Efficient mostly only until the first init process
    \item Userspace initialization remains a significant challenge
    \end{itemize}
  \item Beyond Booting: Restoring Systems from Suspend to Ram:
    \begin{itemize}
    \item An alternative to booting for instant system readiness
    \item Avoids the need for userspace initialization
    \end{itemize}
  \end{itemize}
\end{frame}

\begin{frame}{Challenges of Suspend to RAM for Instant System
    Readiness}
  \begin{itemize}
  \item Ensuring the integrity of memory and hardware state upon
    resume
  \item Consuming as little power as possible to maintain the system
    in suspend for sufficient time
  \item Achieving a fast resume time
  \item Finding the correct balance between these three factors is
    a difficult task
  \end{itemize}
\end{frame}

\begin{frame}{Overview of this talk}
  \begin{itemize}
\item \textbf{Hardware \& Low-Level Firmware Overview}
  \begin{itemize}
  \item TI DRA821 SoC (Jacinto family)
  \item Components (firmware/hardware) involved in S2R
  \end{itemize}

\item \textbf{Implementing S2R Support}
  \begin{itemize}
  \item Techniques and strategies for TI DRA821 SoC
  \end{itemize}

\item \textbf{Future Challenges \& Improvements}
  \begin{itemize}
  \item Addressing obstacles and enhancing S2R performance
  \end{itemize}
  \end{itemize}
\end{frame}

  % \item Hardware overview of the TI DRA821
  % \item Integrating S2R on the SoC
  % \item Future challenge and improvement

\section{Hardware overview of the\\TI DRA821}

\begin{frame}{Jacinto Global Architecture}
    \begin{columns}
    \column{0.4\textwidth}
    \begin{itemize}
      \item K3 family: multicore SoC architecture platform
      \item Designed for low power, high performance and high integrated device architecture
      \item Jacinto is part of the K3 family and targets automotive
    \end{itemize}
    \column{0.6\textwidth}
    \begin{center}
      \includegraphics[width=1\textwidth]{DRA821_Overview.png}
    \end{center}
  \end{columns}
\end{frame}

\begin{frame}{TI DRA821 SoC Architecture: Multicore Processor Overview}
  \begin{columns}
    \column{0.6\textwidth}
    \begin{center}
      \includegraphics[width=1\textwidth]{DRA821_Overview.png}
    \end{center}
    \column{0.4\textwidth}
    \begin{itemize}
    \item 2 Cortex A72
      \begin{itemize}
      \item ARM 64 bits
      \item MAIN domain
      \item Linux, TF-A, U-Boot
      \end{itemize}
    \item 2x2 Cortex R5
      \begin{itemize}
      \item ARM 32 bits
      \item 2 in MAIN domain
      \item 2 in MCU domain
      \item DM firmware, U-Boot and custom firmwares
      \end{itemize}
    \item 1 cortex M3
      \begin{itemize}
      \item ARM 32 bits
      \item WKUP domain
      \item Secure firmware
      \end{itemize}
    \end{itemize}
  \end{columns}
\end{frame}

\begin{frame}{Beyond the SoC: PMIC \& DDR in Suspend to RAM}
  \begin{columns}
    \column{0.5\textwidth}
    \begin{itemize}
      \item Power Management IC (PMIC)
      \begin{itemize}
      \item Powers SoC and DDR
      \item Handles wake-up in deep suspend to RAM
      \item Implementation differences (one or two PMICs)
      \end{itemize}
    \end{itemize}

    \column{0.5\textwidth}
    \begin{itemize}
        \item DDR Memory
          \begin{itemize}
          \item Retains data during suspend
          \item Independent of DDR controller during suspend
          \end{itemize}
    \end{itemize}
  \end{columns}
\end{frame}

\begin{frame}{Active \& MCU Low Power Modes}

\begin{itemize}
\item Active Mode (Normal Mode)
  \begin{itemize}
  \item All cores and power domains powered on
  \item PM actions: runtime PM, DVFS, AVFS, CPU idle...
  \end{itemize}

\item MCU Mode
  \begin{itemize}
  \item A72 cores and MAIN power domain shut down
  \item Controllers in MAIN power domain also off
  \end{itemize}
\end{itemize}

\end{frame}

\begin{frame}{Advanced Low Power Modes}
\begin{itemize}
\item I/O Retention Mode (Unofficial Name)
  \begin{itemize}
  \item Entire SoC OFF except for a small part managing wake-up GPIOs
  \end{itemize}

\item OFF Mode
  \begin{itemize}
  \item SoC completely off
  \item PMIC as the only wake-up source
  \end{itemize}
\end{itemize}

\end{frame}

\begin{frame}{Boot sequence: cores and firmwares involved}
  \begin{columns}
    \column{0.8\textwidth}
    \begin{center}
      \includegraphics[width=1.0\textwidth]{graphics/sequence-j7200.pdf}
    \end{center}
    \column{0.3\textwidth}
    \begin{itemize}
      \item TI Foundational Security: hardware firewall, CPU control (closed source)
      \item Device Manager firmware: clock and pin control
      \item Communication to DM and TIFS through TISCI(API)
    \end{itemize}
  \end{columns}
\end{frame}

\section{Integrating S2R on the SoC}

\begin{frame}{Overall Suspend and Resume Sequence}
  \begin{columns}
    \column{0.5\textwidth}
      \includegraphics[height=0.9\textheight]{graphics/s2r_j7200_suspend_sequence.pdf}
    \column{0.5\textwidth}
      \includegraphics[height=0.9\textheight]{graphics/s2r_j7200_resume_sequence.pdf}
  \end{columns}
\end{frame}

\begin{frame}{Linux Suspend \& Resume Implementation}
  \begin{columns}
    \column{0.5\textwidth}
    \begin{itemize}
    \item Standard sequence through TF-A (Trusted Firmware A)
    \end{itemize}
    \begin{itemize}
    \item Driver-specific considerations
      \begin{itemize}
      \item General assumption: controller not completely off
      \item Reset sequences required for each resume
      \item Save and restore register values or configurations
      \end{itemize}
    \end{itemize}
    \column{0.4\textwidth}
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_suspend_sequence-Linux.pdf}
    \\
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_resume_sequence-Linux.pdf}
  \end{columns}
\end{frame}

\begin{frame}{Handling TF-A for Suspend \& Resume}
  \begin{columns}
    \column{0.6\textwidth}
    \begin{itemize}
    \item TF-A resides in SRAM by default
    \item Challenge: SRAM data loss during SoC OFF
    \end{itemize}
    \begin{itemize}
    \item Solution: Save \& restore TF-A memory
      \begin{itemize}
      \item Reuse \texttt{bl31\_warm\_entrypoint} function in TF-A
      \item Pass resume address for resuming
      \end{itemize}
    \end{itemize}
    \begin{itemize}
    \item Initial implementation: Copy full SRAM content to DDR and restore during boot
    \end{itemize}
    \column{0.4\textwidth}
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_suspend_sequence-TFA.pdf}
    \\
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_resume_sequence-TFA.pdf}
  \end{columns}
\end{frame}


\begin{frame}{Navigating TF-A Firewall Limitations for Resume}
  \begin{columns}
    \column{0.5\textwidth}
    \begin{itemize}
    \item TIFS Firewall Restoration Limitations
      \begin{itemize}
      \item Hardware firewall installation: configured only if the image is signed
      \end{itemize}
    \end{itemize}
    \begin{itemize}
    \item Memory Management Adjustment
      \begin{itemize}
      \item Save context instead of full memory
      \end{itemize}
    \end{itemize}
    \begin{itemize}
    \item TF-A Cold Boot Process
      \begin{itemize}
      \item Early check: resume or standard boot?
      \item Restore context and jump to resume function (if resume)
      \end{itemize}
    \end{itemize}
    \column{0.5\textwidth}
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_suspend_sequence-TFA2.pdf}
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_resume_sequence-TFA2.pdf}
  \end{columns}
\end{frame}


\begin{frame}{DM Firmware Adaptations for Suspend Part}
  \begin{columns}
    \column{0.65\textwidth}
    \begin{itemize}
    \item Final software executing before SoC shutdown
    \item Responsibilities:
      \begin{itemize}
      \item Put DDR into self-refresh to maintain data integrity
      \item Send suspend sequence to PMIC for power management and wake-up handling
      \end{itemize}
    \item Code moved to SRAM
      \begin{itemize}
      \item Addressing DDR self-refresh limitation
      \item Guaranteeing correct execution of the code
      \end{itemize}
    \item Storing essential data for resume
      \begin{itemize}
      \item Magic number in PMIC register for SPL resume detection
      \item TF-A resume address in DDR (removed with cold boot TF-A)
      \end{itemize}
    \end{itemize}
    \column{0.4\textwidth}
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_suspend_sequence-DM.pdf}
  \end{columns}
\end{frame}

\begin{frame}{DM Firmware's Role in Resume \& Linux Context Management}
  \begin{columns}
    \column{0.7\textwidth}
    \begin{itemize}
    \item No special adaptations required during the resume process
    \item Prerequisite: Devices managed by DM firmware deactivated by Linux during suspend
      \begin{itemize}
      \item Ensuring smooth device activation during resume
      \end{itemize}
    \item Linux handles context and device activation
      \begin{itemize}
      \item Efficiently managing the resume process for DM firmware
      \end{itemize}
    \item DM firmware boots normally after resuming, with no additional steps needed
    \end{itemize}
    \column{0.4\textwidth}
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_resume_sequence-DM.pdf}
  \end{columns}
\end{frame}

\begin{frame}{U-Boot SPL Changes \& Optimizations During Resume}
  \begin{columns}
    \column{0.6\textwidth}
    \begin{itemize}
    \item U-Boot SPL changes only during resume
    \item SPL on R5 core involved in resume process
      \begin{itemize}
      \item Detects resume by checking PMIC value
      \item Exits DDR from retention instead of configuring
      \end{itemize}
    \item TF-A \& DM Firmware Image Reloading
      \begin{itemize}
      \item Initially restored TF-A to SRAM from DDR
      \item Now reloads TF-A image and DM firmware image
      \end{itemize}
    \item Optimization: Load from DDR instead of storage re-read
    \end{itemize}
    \column{0.5\textwidth}
    \includegraphics[width=1\textwidth]{graphics/s2r_j7200_resume_sequence-SPL.pdf}
  \end{columns}
\end{frame}


\section{Future challenge and improvement}

\begin{frame}{Recent Cache Management Improvement}
  \begin{itemize}
  \item L3 cache disabled initially to avoid resume issues
  \item Issue: Unflushed cache causing outdated DDR data
  \item L3 cache management at SoC level
    \begin{itemize}
    \item Access to specific registers required
    \item Firewall prevented DM firmware register modification
    \end{itemize}
  \item TIFS update needed and completed recently
  \end{itemize}
\end{frame}

\begin{frame}{Security Vulnerabilities in Current Implementation}
  \begin{itemize}
  \item Challenges: Security weaknesses
  \item Feedback from TF-A developers
  \item SPL image trust issues during resume
    \begin{itemize}
    \item TF-A community's perspective
    \end{itemize}
  \item Current implementation concerns
    \begin{itemize}
    \item TF-A context accessibility during resume
    \item Hardware firewall applied too late
    \end{itemize}
  \end{itemize}
\end{frame}

\begin{frame}{Enhancing Security with TF-A Context Encryption}
  \begin{itemize}
  \item Encrypt TF-A context during suspend
    \begin{itemize}
    \item Protecting data integrity and confidentiality
    \end{itemize}
  \item TIFS as encryption/decryption candidate
    \begin{itemize}
    \item New feature requirements
    \item Limitations: PMIC access, DDR availability
    \end{itemize}
  \end{itemize}
\end{frame}

\begin{frame}{A Collaborative Approach for Secure TF-A Decryption}
  \begin{itemize}
  \item Solution: SPL and new TISCI call for decryption during resume
    \begin{itemize}
    \item SPL's role: Exiting DDR from retention
    \item TIFS's role: Decrypting TF-A after SPL's action
    \end{itemize}
  \item Ensuring secure collaboration between SPL and TIFS
  \end{itemize}
\end{frame}


\begin{frame}{Firmware Management During Suspend to RAM}
  \begin{itemize}
  \item Challenge: Handling firmware on R5 cores
    \begin{itemize}
    \item Firmware self-management
      \begin{itemize}
      \item Free and stop devices during suspend
      \item Get and restore devices during resume
      \item Save/restore SRAM in/from DDR if used
      \item Notification about entering suspend
      \end{itemize}
    \item Alternative: Firmware unaware of system suspend
      \begin{itemize}
      \item Device management by another component (e.g., DM firmware)
      \item Restore firmware context addresses
      \end{itemize}
    \end{itemize}
  \item Linux communication
    \begin{itemize}
    \item Restore communication channels by Linux kernel
    \end{itemize}
  \end{itemize}
\end{frame}

\begin{frame}{Convergence of Suspend to RAM Support for K3 Family SoCs}
  \begin{itemize}
  \item DRA821 not unique in K3 family
  \item Default suspend to RAM support for other K3 SoCs
    \begin{itemize}
    \item Does not use OFF mode
    \end{itemize}
  \item Plan: Enable OFF mode support for some SoCs
    \begin{itemize}
    \item Maintain common code for I/O retention cases
    \end{itemize}
  \item Goal: Convergence and shared implementation
  \item Ongoing effort
  \end{itemize}
\end{frame}

\questionslide

\end{document}